1. Field of the Invention
The present invention generally relates to a method of manufacturing a contact hole of a semiconductor device, and more particularly, the present invention relates to a method of manufacturing a contact hole of a semiconductor device in which an entire etching process can be advantageously controlled by setting a first etch point according to a CN (carbonxe2x80x94nitrogen) emission spectrum originated from a spacer during the etching process.
2. Description of the Related Art
In initially developed VLSI (very large scale integration) devices, polysilicon gates were typically adopted due to their favorable electrical characteristics, reliability, integration degree and the like.
Since polysilicon is a material having a high melting point, a self-align method can be applied in which source and drain diffusion regions are simultaneously formed during the manufacture of the gate electrode. In addition, polysilicon can be thermally oxidized after being patterned as the polysilicon gate electrode. Accordingly, damage generated at the edge portions of the gate electrodes by a reactive ion etching can be contained, and device reliability can be increased by relaxing the high fringe electric field at the edge portions when an electric potential is applied to the gate electrode.
However, for devices having a polysilicon gate and a design rule of 1 xcexcm or less, an increased operational speed for the device which typically results from integration is eliminated. In addition, a problem of retarding signal transfer occurs due to an increase in a wire resistance of the minute device and an increase in capacitance through a reduction of a wiring pitch. Further, since polysilicon has a relatively large resistance when compared with other conductive materials, a frequency characteristic of the device is deteriorated.
Therefore, silicide compounds having a high melting point have recently been utilized as a gate electrode material. The silicide compounds have characteristics similar to polysilicon and have a lower resistance by one-tenth or less. Typically, tungsten silicide is utilized as the silicide compound.
Recently developed high-integrated semiconductor devices have a design rule as small as about 0.15 xcexcm. Accordingly, the size of a contact hole, which is an electric contacting portion with silicon, has been gradually reduced, and the BC processing margin for an interconnection of a storage node with source/drain regions of a transistor has been further limited.
Presently, a self-align method is utilized for confirming the BC processing margin and a spacer is formed at side surfaces of a gate electrode for preventing a connection of the gate electrode with the storage node. However, confirmation of the BC processing margin is still a serious problem. Likewise, it is important to confirm the thickness of the spacer formed on the side surface of the gate electrode, that is, the shoulder margin.
FIGS. 1A through 1E are cross-sectional views for explaining a conventional method of manufacturing a contact hole of a semiconductor device.
Referring to FIG. 1A, a first oxide layer 120 is formed by a local oxidation of silicon (LOCOS) method on an active region on a semiconductor substrate 100. The active region is defined between field regions, which in turn are defined by field oxide layers 110 having a thickness of about 1800-2000 xc3x85. Then, a first conductive layer 130 is formed on the first oxide layer 120 by depositing a conductive material to a thickness of about 800-1200 xc3x85. The conductive material of the first conductive layer 130 may be formed of an impurity-doped conductive polysilicon.
Next, a second conductive layer 140 is formed on the first conductive layer 130. The second conductive layer 140 is formed by depositing a metal-silicide such as tungsten silicide (WSix), tantalum suicide (TaSi2), molybdenum silicide (MoSi2), etc. to a thickness of about 1300-1700 xc3x85.
A first insulating layer 150 is formed on the second conductive layer 140. The first insulating layer 150 is formed by depositing a nitride compound such as silicon nitride (SiN) to a predetermined thickness by a plasma enhanced chemical vapor deposition method. The first insulating layer 150 passivates (protects) the second conductive layer 140 during an etching process and an ion implantation process implemented afterward.
Then, a second oxide layer 160 is formed on the first insulating layer 150. The second oxide layer 160 is formed by depositing a hot temperature oxide (HTO) such as silicon oxide to a predetermined thickness by a low pressure chemical vapor deposition method. The second oxide layer 160 functions as an etching stopper during an etching process implemented afterward.
Referring to FIG. 1B, a photoresist pattern is formed by coating photoresist on the second oxide layer 160 to form a photoresist layer (not shown) and then by patterning the photoresist using photolithography techniques. The photoresist pattern (not shown) is used to define later-formed gate electrodes.
Then, the second oxide layer 160, the first insulating layer 150, the second conductive layer 140, the first conductive layer 130 and the first oxide layer 120 are subsequently and anisotropically etched by utilizing the photoresist pattern as an etching mask to form a gate electrode 170. The gate electrode 170 include a gate oxide layer 122, a first conductive pattern 132, a second conductive pattern 142, a first insulating layer pattern 152 and a second oxide layer pattern 162.
Referring to FIG. 1C, a second insulating layer (not shown) is formed on the semiconductor substrate 100 (on which the gate electrode 170 is formed) by depositing silicon nitride. Then, an etch back process is implemented until the active region of the semiconductor substrate 100 is exposed to thereby form spacers 180 on the side of the gate electrode 170. At this time, the second oxide layer pattern 162 formed from the high temperature oxide functions as an etching stopper during the etch back of the second insulating layer.
Next, an ion implantation process is implemented to implant impurities into the exposed active region of the semiconductor substrate 100 to form a diffusion region 112 of a source/drain region of a transistor. During the ion implantation process, the spacers 180 formed on both side portions of the gate electrode 170 function as a mask.
Referring to FIG. 1D, a dielectric interlayer 190 is formed on the semiconductor substrate 100 on which the gate electrode 170 and the spacers 180 are formed. The dielectric interlayer 190 is formed by depositing silicon oxide, BPSG, PSG, or the like, using a low pressure chemical vapor deposition method or plasma enhanced chemical vapor deposition method. Subsequently, a photoresist pattern 200 is formed by coating photoresist on the dielectric interlayer 190 and by patterning the photoresist using conventional photolithography techniques. The photoresist pattern 200 defines contact holes to be formed later.
Referring to FIG. 1E, the dielectric interlayer 190 is etched by utilizing the photoresist pattern 200 as an etching mask to expose the source/drain region 112 on the semiconductor substrate 100, thereby forming a contact hole 210 and a dielectric interlayer pattern 192. The etching of the dielectric interlayer layer is implemented using etching equipment having a high ionization degree such as ICP, TCP, SWP, DRM, etc., and by utilizing a mixture gas having a high ratio of carbon/fluorine such as C3F8, C4F8, CO, etc.
Then, a conductive material is deposited onto the substrate 100 (on which the dielectric interlayer pattern 192 including the contact hole 210 is formed) to form a contact or a storage node (not shown).
The above-described method of forming a contact hole suffers a drawback as will be explained below with reference to FIG. 2.
In order to manufacture a semiconductor device, various layers of metals, oxides, polysilicon, etc., are subsequently integrated on a semiconductor substrate. Then, a photoresist pattern is formed on the upper most layer, and a dry etching process utilizing plasma is implemented to dry etch the exposed portion of the upper most layer.
The etching of the dielectric interlayer for the formation of the contact hole is implemented using equipment having a high ionization degree such as ICP, TCP, SWP, DRM, etc., and by utilizing a mixture gas having a high carbon/fluoride ratio such as C3F8, C4F8, CO, etc. Generally, the etching ratio of the dielectric interlayer spacer is larger than 8:1. If the etching ratio is increased, the etching might be stopped during the implementation thereof, and if the etching ratio is decreased, a selective etching is not accomplished.
The etching of the dielectric interlayer for forming the contact hole is stopped when the dielectric interlayer designated as the thickness B of FIG. 2 is etched. Generally, the etching is implemented with an optimized time condition. Here, the thickness designated as A, which is obtained by substracting the thickness of the gate electrode 170 from B, is different between wafers and lots. The difference is about 1000 xc3x85. Accordingly, when the etching is implemented with a constant time condition, an excessive over etching or an under etching can occur. As a result, incompletely etched contact hole can be manufactured to thereby increase a failure ratio and deteriorate the quality (or reliability) of the semiconductor device.
Etching methods applied in the manufacture of semiconductor device are classified as either a wet etching method or a dry etching method. Also, the removal of a target material by dry etching is classified in two manners. The target material is removed through a chemical reaction with an active particulate or through a physical impaction. If plasma is generated, the chemical reaction is further activated.
Dry etching consists of a main etching by which the upper most layer is etched to the end point thereof and an over etching by which a specific portion of the upper most layer which has not been completely etched due to a thickness difference is etched. The over etching is implemented after carrying out EPD (end point detection) for measuring the time needed for the main etching by which the upper most layer is etched to the end point.
A specific material formed on the semiconductor substrate is selectively etched through a reaction with plasma. During the etching process, a light having a specific wavelength is emitted. The wavelength of the emitted light is dependent on the kind of the plasma and the material to be etched.
The light having the specific wavelength is utilized to detect the end point of the dry etching. That is, the light emitted by the layer formed under the target layer is detected to end the dry etching process.
However, the thickness of the target layer to be etched is not uniform throughout the whole wafer due to the presence of on or more surface steps, etc., and the etching is not uniformly implemented throughout the whole wafer. Accordingly, sufficient time is needed to completely etch the desired portion of the target layer.
However, because the etchant utilized for the plasma etching also has a selectivity ratio as for the case of the wet etching, a long-lasting etching might undesirably etch the underlying layer after completely etching the target layer. When the etchant having a lower selectivity ratio is used in order to increase the etching efficiency, the above-described phenomenon might occur more frequently.
Therefore, in order to solve the problem, a method of changing the etching condition by detecting a specific point is additionally utilized with the method of implementing the plasma etching during a given time period. That is, the etching is implemented by utilizing the condition by which the etching is rapidly carried out before the specific point, and then, the etching is implemented by utilizing the condition having a high selectivity with respect to the underlying layer even though the etching rate is lowered after the specific point.
At this time, the specific point denotes the time when the underlying layer positioned under the target layer is exposed, and the EPD finds this specific point. Further, the etching implemented before this specific point is called as xe2x80x9cmain etchingxe2x80x9d and the etching implemented after this specific point is called as xe2x80x9cover etching.xe2x80x9d
The EPD plays an important role for the etching process implemented through multi-step processes. Various methods are utilized for the EPD. However, the method of detecting an emission generated from plasma by means of a monochromator in a processing chamber is widely used. Through this method, some peaks are detected from a light having a specific wavelength for a target material.
Japanese Patent Laid-open No. Hei 3-183162 discloses a method of forming a contact hole by etching an insulating layer of a three-layered structure of an oxide layer, a nitride layer and an oxide layer on gate electrodes and side walls. In this Patent, the inter layer, that is, the nitride layer is utilized as a detecting layer of the end point of the etching so as to control the etching process.
Japanese Patent Laid-open No. Hei 4-32227 discloses a method of determining an end point of etching for a specific layer by forming a silicon nitride layer under a specific layer and then detecting a CN emitting spectrum generated from the silicon nitride layer during a dry etching.
It is an objective of the present invention to provide a method of manufacturing a contact hole of a semiconductor device by which an optimized etching condition can be obtained using EPD and a product quality can be improved by applying an optimized etching condition for each wafer.
To accomplish this objective, a method of manufacturing a contact hole of a semiconductor device is provided in which a spacer is formed on a side wall of a gate electrode formed on a substrate, and then a dielectric interlayer is formed thereon. A predetermined region of the dielectric interlayer is etched using an etching gas. Particularly, a first etching is implemented until an emitting amount of a chemical compound produced by the etching gas with the spacer becomes maximum, and then a second etching is implemented until the substrate is exposed.
The objective of the present invention also is accomplished by a method of manufacturing a contact hole of a semiconductor device in which a spacer is formed on a gate electrode formed on a substrate, and then an SiN layer is formed on an exposed portion of the substrate. A dielectric interlayer is formed on the thus obtained substrate. Then, a predetermined region of the dielectric interlayer is etched by using an etching gas. Particularly, a first etching is implemented until an emitting amount of a chemical compound produced by the etching gas with the spacer becomes a maximum, and then a second etching is implemented until the substrate is exposed.